1. Field of the Invention
This invention relates generally to non-volatile electrically erasable CMOS memory cells and more particularly, it relates to an improved control gate-addressed CMOS memory cell which allows for programming and erasing by tunneling through the gate oxides of the PMOS and NMOS transistors.
2. Description of the Prior Art
A conventional prior art CMOS memory cell having a PMOS transistor and an NMOS transistor with a common floating gate is illustrated and described in U.S. Pat. No. 4,885,719 to D. J. Brahmbhatt issued on Dec. 5, 1989, and in U.S. Pat. No. 5,272,368 to J. E. Turner et al. issued on Dec. 21, 1993, which are both herein incorporated by reference. In FIG. 1 of the drawings of the present application, there is shown a schematic of a CMOS memory cell which is similar to the one in either the '719 patent or the '368 patent.
The CMOS memory cell 100 is comprised of a complementary metal-oxide silicon (CMOS) electrically erasable (E.sup.2) transistors. As can be seen, the source of the PMOS transistor 102 is connected to a first power supply VCC and the source of the NMOS transistor 104 is connected to a second power supply potential VSS. The drains of the two transistors 102 and 104 are connected together at a common node 124 which forms the output of the CMOS memory cell 100. The two CMOS transistors also have a common floating gate 126 which can be electrically programmed by the tunneling of electrons through a tunnel oxide separating the floating gate from a programming or write node 134. The tunnel oxide is represented by a capacitor 108. An NMOS transistor 110 supplies a word control (WC) voltage or programming potential to the capacitor 108 as controlled by a word line (WL) voltage applied to its gate. A capacitor 106 separates the floating gate 126 from an array control gate (ACG) node.
While the CMOS memory cell 100 utilizes essentially zero power when it is not changing states, it does suffer from the disadvantage of requiring a second capacitor 108 with a tunnel oxide region which thus requires additional amounts of space on the die. Moreover, since the second capacitor 108 includes n+ implant regions formed in a p type substrate and a gate oxide overlying the implant region, a programming junction region is required to be added to the substrate beneath the gate oxide in order to prevent depletion of the p type substrate during programming. Thus, the fabrication of the memory cell 100 involves additional steps according to known techniques on a silicon substrate.
Another prior art CMOS memory cell having a PMOS transistor and an NMOS transistor sharing a common floating gate is illustrated and described in application Ser. No. 08/427,117 entitled "A CMOS Memory Cell With Gate Oxide of Both NMOS and PMOS Transistors as Tunneling Window for Program and Erase" and filed on Apr. 21, 1995, in the names of Jonathan Lin and Bradley A. Sharpe-Geisler. This Ser. No. 08/427,117 is assigned to the same assignee as the present invention and is hereby incorporated by reference. In FIG. 2 of the drawings of the present application, there is shown a schematic of a CMOS memory cell 300 which is similar to the one in Ser. No. 08/427,117.
The CMOS memory cell 300 includes a PMOS transistor 302 and an NMOS transistor 304 which share a common floating gate 305. The drains of the transistors 302 and 304 are coupled together at a node 307 so as to form the output of the CMOS memory cell 300. The CMOS memory cell 300 further includes a single capacitor 306 connected to couple a voltage from an array control gate (ACG) node to the floating gate 305. A separate PMOS pass transistor 310 has its drain connected to the source of the PMOS transistor 302, its source connected to receive a word control (WC) voltage and its gate connected to receive a word line (WL) voltage.
In order to erase the CMOS memory cell 300, a voltage of +13.8 volts is applied to the array control gate (ACG) node of the capacitor 306 and the source of the NMOS transistor 304 is connected to a ground potential or zero volts. As a result, electrons will tunnel from the source of the transistor 304 through the gate oxide to the common floating gate 305. Further, a high impedance is applied to the source of the PMOS transistor 302 during erase to prevent depletion of its channel which would occur if the PMOS transistor 302 were biased to add electrons to the floating gate 305. Nevertheless, the CMOS cell 300 suffers from the disadvantage that it is still susceptible to a potential deep depletion related disturb problem. This is caused by the fact that even though the transistor 310 is turned off and isolates the WC voltage from the source of the transistor 302 the transistors 310 and 302 have the same substrate voltage. It is generally desired to have the transistor 302 in deep depletion in order for the cell to be not disturbed. Thus, if the voltage on the substrate is switched high, then the transistor 302 may come out of deep depletion too fast and go into an inversion so as to cause disturb by tunneling electrons through the gate oxide of the transistor 302.
The present invention represents a significant improvement over the aforementioned '719 and '368 patents and the application Ser. No. 08/427,117 so as to provide an improved CMOS memory cell having a smaller cell size than those traditionally available. This is achieved by utilizing a control gate node to address the PMOS and NMOS transistors in the memory cell so as to allow for both programming and erasing by tunneling through their gate oxides.